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EECS 150 Spring 2012 Checkpoint 3: Caches Prof. John Wawrzynek TAs: James Parker, Daiwei Li, Shaoyi Cheng Department of Electrical Engineering and Computer Sciences College of Engineering, University of California, Berke
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Document Date: 2012-04-06 00:22:32

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File Size: 206,13 KB

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Company

Checkpoint / Xilinx / /

Event

Product Issues / Product Recall / /

Facility

New Files This checkpoint / Read Stall / University of California / Computer Sciences College of Engineering / /

IndustryTerm

software/mmult/ / cache services / /

Organization

University of California / Berkeley / Shaoyi Cheng Department of Electrical Engineering / Electrical Engineering and Computer Sciences College of Engineering / /

Person

John Wawrzynek / Shaoyi Cheng / James Parker / /

Position

Driver / MIG Memory Arbiter / memory arbiter / DDR2 controller / controller / arbiter / /

Product

system / DDR2 memory interface / Xilinx DDR2 / /

ProgrammingLanguage

C / Verilog / /

ProvinceOrState

California / /

Technology

FPGA / RAM / rdf / Verilog / UART / /

URL

http /

SocialTag